Publications

Papers

International Journals

An adaptive cache replacement policy based on fine-grain reusability monitor
Duk-Jun Bang, Min-Kwan Kee, Hong-Yeol Lim, and Gi-Ho Park
IEICE Electronic Express, vol. 15, no. 2, pp. 20171099, 2018.

Triple Engine Processor (TEP): A Heterogeneous Near-Memory Processor for Diverse Kernel Operations
Hong-Yeol Lim and Gi-Ho Park
Acm Transactions On Architecture And Code Optimization, no. 14, issue C, 2017.

Sensor data compression and power management scheme for low power sensor hub
Seung-jin Lee, Minkwan Kee and Gi-Ho Park
IEICE Electronic Express, vol. 14, no. 23, pp. 20170974, 2017.

NVM Way Allocation Scheme to Reduce NVM Writes for Hybrid Cache Architecture in Chip-Multiprocessors
Ju-Hee Choi and Gi-Ho Park
IEEE Transactions on Parallel and Distributed Systems, vol. 28, no. 10, pp. 2896-2910, 2017.

An analytical model based on performance demand of workload for energy-efficient heterogeneous multicore systems
Minkwan Kee, Hong-Yeol Lim, Gi-Ho Park, and Sangyeun Cho
Journal of Parallel and Distributed Computing, vol. 100, pp. 172–180. 2017.

Cooperative cache memory (CCM) based on the performance efficiency for 3D stacked memory system
Hong-Yeol Lim and Gi-Ho Park
IEICE Electronic Express, vol. 13, no. 12, pp. 20160276, 2016.

Demand-aware NVM capacity management policy for hybrid cache architecture
Ju-Hee Choi and Gi-Ho Park
The Computer Journal, vol. 59, issue 5, pp. 685-700, 2016.

Data Classification Management with its Interfacing Structure for Hybrid SLC/MLC PRAM Main Memory
Sung-In Jang, Su-Kyung Yoon, Ki-Hyun Park, Gi-Ho Park, and Shin-Dug Kim
The Computer Journal, vol. 58, issue 11, pp. 2852-1863, 2015.

Accelerating Application Start-up with Nonvolatile Memory in Android Systems
Hyo-Jong Kim, Hong-Yeol Lim, Manatunga Dilan, Hyesoon Kim, and Gi-Ho Park
IEEE Micro, vol. 35, no. 1, pp. 15-25, 2015.

Adaptive replacement policy for hybrid cache architecture
Ju-Hee Choi and Gi-Ho Park
IEICE Electronic Express, vol. 11, no. 22, pp. 20140946, 2014.

An Adaptive L2 Cache Prefetching Mechanism for Effective Exploitation of Abundant Memory Bandwidth of 3-D IC Technology
Hong-Yeol Lim and Gi-Ho Park
IEICE Electronic Express, vol. 10, no. 16, pp. 20130523, 2013.

Versatile stream buffer architecture to exploit the high memory bandwidth of 3-D IC technology
Hong-Yeol Lim and Gi-Ho Park
IEICE Electronic Express, vol. 10, no. 4, pp. 20120971, 2013.

An instruction-systolic programmable shader architecture for multi-threaded 3D graphics processing
Jung-Wook Park, Hoon-Mo Yang, Gi-Ho Park, Shin-Dug Kim, and Charles C. Weems
Journal of Parallel and Distributed Computing, vol. 70, no. 11, pp. 1110-1118, 2010.

Design and implementation of Performance Analysis Unit (PAU) for AXI-based multi-core System on Chip (SOC)
Hyun-min Kyung, Gi-ho Park, Jong-wook Kwak, Tae-jin Kim, and Sung-Bae Park
Microprocessor and Microsystems, vol. 34, issue 2-4, pp. 102-116, 2010.

Fully Digital Clock Frequency Doubler
Gunok Jung, Gi-Ho Park, Ukrae Cho, and Jae Cheol Son
IEICE Electronics Express, vol. 7, no. 6, pp. 416-420, 2010.

Low-power Embedded Processor Design Using Branch Direction
Gi-Ho Park, Jung-Wook Park, Gunok-Jung, and Shin-Dug Kim
IEICE Transaction on Fundamentals of Electronics, Communications and Computer Science, vol. E92-A, no. 12, pp. 3180-3181, 2009.

An integrated mapping table for hybrid FTL with fault-tolerant address cache
Jung-Wook Park, Seung-Ho Park, Gi-Ho Park, and Shin-Dug Kim
IEICE Electronics Express, vol. 6, no. 7, pp. 368-374, 2009.

A Way Enabling Mechanism Based on the Branch Prediction Information for Low Power Instruction Cache
Gi-Ho Park, Jung-Wook Park, Hoi-Jin Lee, Gunok Jung, Sung-Bae Park, and Shin-Dug Kim
IEICE Transaction on Electron, vol. E92-C, no. 4, pp. 517-521, 2009.

Low-power Embedded Processor Design Using Branch Prediction
Gi-Ho Park, Jung-Wook Park, Gunok-Jung, and Shin-Dug Kim
IEICE Transaction on Fundamentals of Electronics, Communications and Computer Science, vol. E92-A, no 12, 2009.

Sub-grouped superblock management for high-performance flash storages
JungWook Park, Gi-Ho Park, Charles Weems, and ShinDug Kim
IEICE Electronics Express, vol.6, no. 6, pp. 297-303, 2009.

Power and Skew Aware Point Diffusion Clock Network
Gunok Jung, Chunghee Kim, Kyoungkuk Chae, Giho Park, and Sung Bae Park
IEICE Transaction on Electron, vol. E91-C, no. 11, pp. 1832-1834, 2008.

Cooperative Cache System: A Low Power Cache System for Embedded Processors
Gi-Ho Park, Kil-Whan Lee, Tack-Don Han, and Shin-Dug Kim
IEICE Transaction on Electron, vol. E90-C, no. 4, pp. 708-717, 2007.

A deterministic way-prediction scheme using power-aware replacement policy
Jung-Wook Park, Gi-Ho Park, Sung-Bae Park, and Shin-Dug Kim
Microprocessor and Microsystems, vol. 30, no. 4, pp. 209-215, 2006.

Sim-ARM1136: A case study on the accuracy of the cycle-accurate simulator
Sung-Woo Chung, Gi-Ho Park, Hyo-Joong Suh, Han-Jong Kim, Jung-Bin Im, Jung-Wook Park, and Sung-Bae Park
Microprocessor and Microsystems, vol. 30, no. 3, pp. 137-144, 2006.

A New NAND-type Flash Memory Package with Smart Buffer System for Spatial and Temporal Locality
Jung-Hoon Lee, Gi-Ho Park, and Shin-Dug Kim
Journal of Systems Architecture, vol 51, issue 2, pp. 111-123, 2005.

A Low-Power Branch Predictor for Embedded Processors
Sung-Woo Chung, Gi-Ho Park, and Sung-Bae Park
IEICE Transactions on Information Systems, vol. E87-D, no. 9, pp. 2253-2257, 2004.

A Low Power Tournament Branch Predictor
Sung-Woo Chung, Gi-Ho Park, and Sung-Bae Park
IEICE Transactions on Information Systems, vol. E87-D, no. 7, pp. 1962-1964, 2004.

Dynamic and Selective Low Power Data TLB System
Jung-Hoon Lee, Gi-Ho Park, and Shin-Dug Kim
Microprocessors and Microsystems, vol. 28, issue 3, pp. 95-105, 2004.

Dual Cache Architecture for Low Cost and High Performance
Jung-Hoon Lee, Gi-Ho Park, and Shin-Dug Kim
ETRI Journal, vol. 25, no. 5, pp. 275-287, 2003.

Dual TLB structure for supporting two page sizes
Jung-Hoon Lee, Jang-Soo Lee, Gi-Ho Park, Kil-Whan Lee, and Shin-Dug Kim
Electronics Letter, vol. 36, no. 8, pp. 705-706, 2000.

Methods to Improve Performance of Instruction Prefetching through Balanced Improvement of Primary Two Performance Factors
Gi-Ho Park, Oh-Young Kwon, Tack-Don Han, Shin-Dug Kim, and Sung-Bong Yang
Journal of Systems Architecture, vol. 44, issue 9-10, pp. 755 - 772, 1998.

Non-referenced Prefetch (NRP) Cache for Instruction Prefetching
Gi-Ho Park, Oh-Young Kwon, Tack-Don Han, and Shin-Dug Kim
IEE Proceedings - Computers and Digital Techniques, vol. 143, issue 1, pp. 37-43, 1996.

International Conferences

Intelligence Boosting Engine (IBE): A hardware accelerator for processing sensor fusion and machine learning algorithm for a sensor hub SoC
Minkwan Kee, Seung-jin Lee, Hyun-su Seon, Jongsung Lee, and Gi-Ho Park
2017 IEEE Symposium in Low-Power and High-Speed Chips (COOL Chips 20), 2017.

JUMPRUN: A Hybrid Mechanism to Accelerate Item Scanning for In-Memory Databases
Hongyeol Lim and Giho Park
2017 IEEE International Conference on Big Data and Smart Computing (BigComp), pp. 231-238, 2017.

A Low-Power Sensor Hub SoC Design with an Intelligence Boost Engine for IoT Applications
Minkwan Kee, Hyun-su Seon, Kyungbae Kim, Jongsung Lee, Sungho Kwon, Cheolho Jeong, Gi-Ho Park
16th International Forum on MPSoC for Software-defined Hardware, 2016.

Hardware Accelerator for Low Power Sensor Hub MCU to Process Sensor Fusion Algorithm
Min-Kwan Kee, Hyun-Su Seon, Sung-ho Kwon, Jong-Sung Lee, and Gi-Ho Park
2015 International SoC Design Conference (ISOCC), pp. 189-190, 2015.

Phase Detection Based Data Prefetching for Utilizing Memory Bandwidth of 3D Integrated Circuits
Hong-Yeol Lim, Min-Kwan Kee, and Gi-Ho Park
2013 IEEE International 3D Systems Integration Conference (3DIC), 2013.

What’s the best processor configuration for power efficient heterogeneous multicore system?
Min-Kwan Kee, Hong-Yeol Lim, Gi-ho Park, and Sang-Yeun Cho
4th Workshop on SoCs, Heterogeneous Architectures and Workloads (SHAW-4), 2013

Performance and Energy-Efficiency Analysis of Hybrid Cache Memory based on SRAM-MRAM
Byung-Min Lee and Gi-Ho Park
2012 International SoC Design Conference (ISOCC), pp. 247-250, 2012.

Versatile stream buffer architecture to exploit high memory bandwidth of 3-D Integration technology
Hong-Yeol Lim, Duck-Jun Bang, and Gi-Ho Park
2012 International Conference on Advanced Information Technolog and Sensor Application (SERSC), 2012

Adaptive prefetching scheme for exploiting massive memory bandwidth of 3-D IC technology
Hong-Yeol Lim and Gi-Ho Park
2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International, 2012.

Building Various Architecture Exploration Environments : System Level Simulator, Emulator, FPGA Prototype Board
Gi-Ho Park, Chang Chang-Hoon Oh, Jong-Wook Kwak, Hyun-Min Kyung, Jung-Bin Im, Sung-Yong Cho,? WooKyeong Jeong, Tae-Jin Kim, and Sung-Bae Park
2nd Workshop on Architectural Research Prototyping (WARP-2007), 2007.

Performance Monitoring Unit Design for an AXI-based Multi-Core SoC Platform
Hyun-Min Kyung, Gi-Ho Park, Jong-Wook Kwak, WooKyeong Jeong, Tae-Jin Kim, and Sung-Bae Park
2007 ACM symposium on Applied computing (SAC’07), pp. 1565-1572, 2007.

Architecture exploration and performance verification environments of multi-core SOC for mobile multimedia embedded systems
Gi-Ho Park, Hyun-Min Kyung, Jung-Bin Im, Jong Wook Kwak, Sung Yong Cho, Chang-Hoon Oh, WooKyeong Jeong, Se-Hyun Yang, Kyoung-Soo Kim, Heung-Chul Oh, Tae-Jin Kim, and Sung-Bae Park
2006 International SoC Design Conference (ISOCC), pp. 195-198, 2006.

Architectural Exploration and Performance Verification Environments for a Multi-Core Embedded SOC Platform Design
Gi-Ho Park, Hyun-Min Kyung, Jung-Bin Im, WooKyeong Jeong, Chang-Hoon Oh, Se-Hyun yang, Han-Jong Kim, Heung-Chul Oh, Tae-Jin Kim, and Sung-Bae Park
2nd Workshop on Architecture Research using FPGA Platforms (WARFP-2006), 2006.

Practice and Experience of an Embedded Processor Core Modeling
Gi-Ho Park, Sung-Woo Chung, Han-Jong Kim, Jung-Bin Im, Jung-Wook Park, Shin-Dug Kim, and Sung-Bae Park
2nd international conference on High Performance Computing and Communications (HPCC’06), pp. 621-630, 2006.

Low-Power Data Cache Architecture by Address Range Reconfiguration for Multimedia Applications
Hoon-Mo Yang, Gi-Ho Park, and Shin-Dug Kim
Advances in Computer Systems Architecture (ACSAC 2006), pp. 574-580, 2006.

ARM1136 Processor Simulator Design for Embedded System Design
Gi-Ho Park, Sung-Woo Chung, Han-Jong Kim, Jung-Bin Im, and Sung-Bae Park
2004 International SoC Design Conference (ISOCC), pp. 320-323, 2004.

Power-aware deterministic block allocation for low-power way-selective cache structure
Jung-Wook Park, Gi-Ho Park, Sung-Bae Park, and Shin-Dug Kim
IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD 2004), pp. 42-47, 2004.

A Selective Filter-Bank TLB System
Jung-Hoon Lee, Gi-Ho Park, Sung-Bae Park and Shin-Dug Kim
2003 International Symposium on Low Power Electronics and Design (ISLPED’03), pp. 312-317, 2003.

A High Performance NAND-Type Flash Memory Package with a Smart Buffer Cache System
Jung-Hoon Lee, Gi-Ho Park, and Shin-Dug Kim
International Conference on Computer, Communication and Control Technologies (CCCT’03), pp. 261-266, 2003.

Application-Specific Data Cache System for High Performance
Jung-Hoon Lee, Gi-Ho Park, and Shin-Dug Kim
ISCA 18th International Conference on Computers and Their Applications (CATA 2003), 2003.

An Adaptive Multi-Module Cache with Hardware Prefetching Mechanism for Multimedia Applications
Jung-Hoon Lee, Gi-Ho Park, and Shin-Dug Kim
11th Euromicro Conference on Parallel, Distributed and Network-Based Processing (PDP’03), pp. 109-116, 2003.

An Advanced Filtering TLB for Low Power Consumption
Jin-Hyuck Choi, Jung-Hoon Lee, Gi-Ho Park, and Shin-Dug Kim
14th Symposium on Computer Architecture and High Performance Computing, pp. 93-99, 2002.

A Power Efficient Cache Structure for Embedded Processors Based on the Dual Cache Structure
Gi-Ho Park, Kil-Whan Lee, Jae-Hyuk Lee, Tack-Don Han, and Shin-Dug Kim
Languages, Compilers, and Tools for Embedded Systems (LCTES 2000), pp. 162-177, 2001.

The Cache Memory System for CalmRISC32
Kil-Whan Lee, Jang-Soo Lee, Gi-Ho Park, Jung-Hoon Lee, Tack-Don Han, Shin-Dug Kim, Yong-Chun Kim, Seh-Woong Jeong, and Kwang-Yup Lee
2nd IEEE Asia Pacific Conference on ASICs (AP-ASIC 2000), p. 323-326, 2000.

A Low-Power Cache System for Embedded Processors
Gi-Ho Park, Kil-Whan Lee, Jang-Soo Lee, Tack-Don Han, Shin-Dug Kim, Yong-Chun Kim, Seh-Woong Jeong, and Kwang-Yup Lee
43rd IEEE Midwest Symposium on Circuits and Systems, pp. 316-319, 2000.

A Dual Data Cache System to Reflect the Principle of Locality Effectively
Gi-Ho Park, Kil-Whan Lee, Tack-Don Han, and Shin-Dug Kim
International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA 2000), 2000.

Cooperative Cache System: A Low-Power Cache Structure for Embedded Processor
Gi-Ho Park, Kil-Whan Lee, Jang-Soo Lee, Jung-Hoon Lee, Tack-Don Han, Moon-Key Lee, Yong-Chun Kim, Seh-Woong Jung, Hyung-Lae Roh, and Kwang-Yup Lee
2000 IEEE Symposium in Low-Power and High-Speed Chips (COOL Chips 3), 2000.

Analyzing Instruction Prefetching Techniques via a Cache Performance Model: Effectivenesses and Limitations
Gi-Ho Park, Tack-Don Han, and Shin-Dug Kim
2000 IEEE International Performance, Computing, and Communications Conference, pp. 501-508, 2000.

An Effective Selection Mechanism to Exploit Spatial Locality in Dual Data Cache
Kil-Whan Lee, Gi-Ho Park, Tack-don Han, and Shin-Dug Kim
International Conference on Computers, Communications and Systems, vol. 98, pp. 31-37, 1998.

An Improved Lookahead Instruction Prefetching
Gi-Ho Park, Oh-Young Kwon, Tack-Don Han, Shin-Dug Kim, and Sung-Bong Yang
High Performance Computing on the Information Superhighway (HPC Asia’97), pp. 712-715, 1997.

Reconfigurable Address Collector and Flying Cache Simulator
Hyung-Min Youn, Gi-Ho Park, Kil-Whan Lee, Tack-Don Han, Shin-Dug Kim, and Sung-Bong Yang
High Performance Computing on the Information Superhighway (HPC Asia’97), pp. 552-556, 1997.

CtrlTile: A Loop Tiling to Reduce Loop Control Overhead
Oh-Young Kwon, Gi-Ho Park, Tack-Don Han, Shin-Dug Kim, and Sung-Bong Yang
15th International Conference on Applied Informatics (IASTED), pp. 13-16, 1997.

Domestic Journals

복수의 엣지 디바이스에서의 CNN 모델 분산 처리를 위한 축소된 분류 모델 활용 기법
김준영, 전종호, 기민관, 박기호
정보과학회논문지, 제 47권 8호, 787-792, 2020.

동적 사상 테이블 기반의 버퍼구조를 통한 Solid State Disk의 쓰기 성능 향상
양훈모, 고소향, 조인표, 박기호, 김신덕
정보처리학회논문지: 컴퓨터 및 통신시스템, 18권 4호, 135-142, 2011.

모바일기기의 웹브라우징 성능 요인 분석
박기호
정보과학회논문지: 컴퓨팅의 실제 및 레터, 17권 2호, 70-82, 2011.

하드웨어 트레이스 생성 시스템의 개발
윤형민, 박기호, 이길환, 한탁돈, 김신덕, 양성봉, 이용석
한국정보처리학회논문지, 5권 3호, 811-823, 1998.

명령어 선인출 기법의 성능 분석에 기반한 성능 증진 기법들
박기호, 권오영, 한탁돈, 김신덕, 양성봉
정보과학회논문지(A), 24권 10호, 1037-1050, 1997.

행렬 곱셈의 지역성 증진을 위한 컴파일러 최적화
권오영, 박준철, 박기호, 한탁돈, 김신덕, 양성봉
정보과학회논문지(B), 23권 12호, 1309-1319, 1996.

미참조 선인출 블럭 캐슁에 의한 효율적인 명령어 선인출 기법
박기호, 한탁돈, 김신덕
정보과학회논문지, 22권 8호, 1263 - 1274, 1995.

Domestic Conferences

Non-Zero Bitmap (NZB) 인덱싱: CNN 모델 등 희소행렬과 밀집행렬이 혼재된 모델을 위한 효율적인 행렬 표현 방식
한치원, 기민관, 박기호
한국정보과학회 2020 한국컴퓨터종합학술대회 논문집, 464-466, 2020.

복수의 엣지 디바이스에서의 CNN 모델 분산 처리를 위한 축소된 분류 모델 활용에 대한 분석
김준영, 전종호, 기민관, 박기호
한국정보과학회 2019 한국컴퓨터종합학술대회 논문집, 290-292, 2019.

엣지 디바이스에서의 효율적인 딥러닝 응용 수행을 위한 성능 분석
김준영, 한치원, 기민관, 박기호
한국정보과학회 2018 한국소프트웨어종합학술대회 논문집, 1713-1715, 2018.

딥러닝 기반 주가 예측 모델의 정확도 향상을 위한 모델 파라미터들의 최적값 분석
전종호, 기민관, 박기호
한국정보과학회 2018 한국소프트웨어종합학술대회 논문집, 1940-1942, 2018.

저전력 센서 허브를 위한 압축기능을 갖는 센서 인터페이스 제어기 구조 설계
이승진, 기민관, 선현수, 이종성, 박기호
한국정보과학회 2016년 동계학술대회 논문집, 312-314, 2016.

저전력 센서 허브를 위한 전력 관리 기법의 효과 분석
선현수, 기민관, 박기호, 권성호, 이종성
한국정보과학회 2016 한국컴퓨터종합학술대회 논문집, 490-492, 2016.

더티 블록을 우선적으로 교체하는 적응적인 최종 계층 캐시 블록 교체 정책
방덕준, 기민관, 박기호
2014 한국정보과학회 제41회 정기총회 및 동계학술발표회, 1052-1058, 2014.

혼합 이종 멀티-코어 구조에서 코어 동작 주파수 민감도에 따른작업 할당 방식 기반 공유 캐시 파티션 기법의 성능 분석
기민관, 방덕준, 임홍열, 박기호
제 20회 한국반도체학술대회, 2013.

Phase Change Memory의 쓰기 전력 소모를 감소시키기 위한 혼합 쓰기 방법
박찬솔, 박기호
CICS 2012 정보 및 제어 학술대회 논문집, 189-190, 2012.

3D 적층 공정의 큰 메모리 대역폭 활용을 위한 스트림 버퍼 기반 적응적 선인출 기법
임홍열, 이병민, 박기호
2011년도 대한전자공학회 추계종합학술대회, 166-169, 2011.

내장 프로세서 기반 고성능 시스템에서의 내부 버스 병목에 의한 시스템 성능 영향 분석
임홍열, 박기호
한국정보과학회 2011 한국컴퓨터종합학술대회 논문집, 38권, 1호, 24-27, 2011.

내장 시스템을 위한 응용 적응적 메모리 시스템 설계 환경
박기호
CICS 2009 정보 및 제어 학술대회 논문집, 407-408, 2009.

A Power Aware Branch Predictor for Embedded Processors
Sung-Woo Chung, Gi-Ho Park, and Sung-Bae Park
제 11회 한국반도체학술대회, pp. 133-134, 2004.

A Tournament Branch Predictor to Reduce the Power Consumption
Sung-Woo Chung, Gi-Ho Park, and Sung-Bae Park
SOC Design Conference, 2003.

Patents

International Patents

US 2019-0056889 A1 MEMORY SYSTEM INCLUDING A NONVOLATILE MEMORY AND A VOLATILE MEMORY, AND PROCESSING METHOD USING THE MEMORY SYSTEM
Gi Ho Park
2019.02.21

US 10140060 B2 Memory system including a nonvolatile memory and a volatile memory, and processing method using the memory system
Gi Ho Park
2018.11.27

US 9411719 B2 Memory system including nonvolatile and volatile memory and operating method thereof
Gi Ho Park
2016.08.09

US 2016-0210234 A1 MEMORY SYSTEM INCLUDING VIRTUAL CACHE AND MANAGEMENT METHOD THEREOF
Gi Ho Park
2016.07.21

US 8948528 B2 Method and apparatus for restoring image by copying memory
Jin Soo Cho, Gi Ho Park, Won Chang Lee, Shi Hwa Lee, Do Hyung Kim, Joon Ho Song
2015.02.03

US 8930630 B2 Cache memory controller and method for replacing a cache block
Gi Ho Park
2015.01.06

US 2014-0237190 A1 MEMORY SYSTEM AND MANAGEMENT METHOD THEROF
Gi Ho Park
2014.08.21

US 8379712 B2 Image search methods for reducing computational complexity of motion estimation
Gi-ho Park, Shin-dug Kim, Cheong-ghil Kim, In-jik Lee, Sung-bae Park
2013.02.19

US 7725641 B2 Memory array structure and single instruction multiple data processor including the same and methods thereof
Gi-Ho Park, Shin-Dug Kim, Jung-Wook Park, Jun-Kyu Park, Sung-Bae Park
2010.05.25

US 7631146 B2 Processor with cache way prediction and method thereof
Gi-ho Park, Hoi-jin Lee
2009.12.08

US 7623406 B2 Accessing semiconductor memory device according to an address and additional access information
Gi-Ho Park, Gun-Ok Jung
2009.11.24

US 7609582 B2 Branch target buffer and method of use
Gi Ho Park
2009.10.27

US 7471574 B2 Branch target buffer and method of use
Gi Ho Park
2008.12.30

US 7305521 B2 Methods, circuits, and systems for utilizing idle time in dynamic frequency scaling cache memories
Gi-ho Park
2007.12.04

US 7227791 B2 Semiconductor memory device including circuit to store access data
Gi-Ho Park
2007.06.05

US 7152170 B2 Simultaneous multi-threading processor circuits and computer program products configured to operate at different performance levels based on a number of operating threads and methods of operating
Gi-ho Park
2006.12.19

US 6549983 B1 Cache memory system and method for managing the same
Tack-don Han, Gi-ho Park, Shin-dug Kim
2003.04.15

US 6272622 B1 Method of and circuit for instruction/data prefetching using non-referenced prefetch cache
Han; Tack-don, Park; Gi-Ho, Kim; Shin-Dug
2001.08.07

JP 4824956 B2 アクセスデータを貯蔵する回路を備えた半導体メモリ装置
朴基豪
2011.09.16

JP 4791714 B2 ダイナミック周波数スケーリングキャッシュメモリの休止時間を利用する方法、回路及びシステム
朴基豪
2011.07.29

JP 4764026 B2 ダイナミック電圧スケーリングによる低消費電力集積回路装置
朴基豪
2011.06.17

JP 4439288 B2 同時多重スレッディングプロセッサ、動作するスレッドの数に基づいて相異なる性能レベルで動作するように構成されるコンピュータプログラム格納媒体及びこれらを動作させる方法
朴基豪
2010.01.15

JP 2008-123479 A SIMD及びそれのためのメモリアレイ構造
朴基豪, 朴星培, 金新徳, 朴柾ウォク, 朴俊圭
2008.05.29

JP 2007-220270 A メモリセルに対するアクセス情報を貯蔵する半導体メモリ装置
朴基豪, 丁健オク
2007.08.30

JP 3899376 B2 キャッシュメモリシステム及びその運用方法
韓鐸敦, 金新徳, 朴基豪
2007.01.12

JP 2007-004835 A キャッシュメモリの運用方法
韓鐸敦, 金新徳, 朴基豪
2007.01.11

JP 2006-134331 A ブランチ目的アドレスを利用してキャッシュウェイを予測するプロセッサ及びその方法
朴基豪, 李會鎭
2006.05.25

JP 2006-031697 A 分岐ターゲットバッファと使用方法
朴基豪
2006.02.02

JP 3628375 B2 未参照先取りキャッシュを利用した命令語先取り方法およびその回路
韓鐸敦, 朴基豪, 金新徳
2004.12.17

CN 001725374 B 包括存储访问数据的电路的半导体存储器件
朴基豪
2012.01.25

CN 100480994 C 分支目标缓冲器及其使用方法
朴基豪
2009.04.22

CN 100394381 C 同步多线程处理器电路以及运行方法
朴基豪
2008.06.11

WO2014-209080 A1 MEMORY SYSTEM INCLUDING VIRTUAL CACHE AND METHOD FOR MANAGING SAME
PARK, Gi Ho
2014.12.31

WO2013-032101 A1 MEMORY SYSTEM AND MANAGEMENT METHOD THEREFOR
PARK, Gi Ho
2013.03.07

WO2012-091234 A1 MEMORY SYSTEM INCLUDING A NONVOLATILE MEMORY AND A VOLATILE MEMORY, AND PROCESSING METHOD USING THE MEMORY SYSTEM
PARK, Gi Ho
2012.07.05

WO2010-140738 A1 CACHE MEMORY CONTROLLER AND METHOD FOR REPLACING A CACHE BLOCK
PARK, Gi Ho
2010.12.09

DE 19533962 A1 Verfahren und Schaltung zum vorauseilenden Holen von Befehlen/Daten mit einem Prefetch-Cache für Befehle/Daten, auf die nicht zugegriffen worden ist
Han, Tack-Don, Park, Gi-Ho, Kim, Shin-Dug
1996.10.24

GB 002426095 B Methods, circuits, and systems for utilizing idle time in dynamic frequency scaling cache memories
PARK GI-HO
2007.11.28

GB 002416234 B Semiconductor memory device including circuit to store access data
PARK GI-HO
2007.05.16

GB 002404055 B Methods, circuits and systems for utilizing idle time in dynamic frequency scaling cache memories
PARK GI-HO
2006.10.11

GB 002416412 B Branch target buffer and method of use
PARK GI-HO
2006.09.20

GB 002410584 B Simultaneous multi-threading processor circuits and computer program products configured to operate at different performance levels
PARK GI-HO
2006.02.01

GB 002398660 B Simultaneous multi-threading processors operating at different performance levels
PARK GI-HO
2005.09.07

GB 002299879 B Method of and circuit for instruction/data prefetching using non-referenced prefetch cache
TACK-DON * HAN, GI-HO * PARK, SHIN-DUG * KIM
2000.02.23

FR 2733065 B1 PROCEDE ET CIRCUIT DE LECTURE ANTICIPEE D’INSTRUTIONS/ DONNEES UTILISANT UN CACHE DE LECTURE ANTICIPEE NON CONSULTE
HAN TACK DON, PARK GI HO, KIM SHIN DUG
1997.12.05

TW I285841 B 分支目標緩衝器、分支目標緩衝器記憶體陣列、分支預測單元及具有分支指令預測功能之處理器
朴基豪
2007.08.21

TW I264002 B 包含儲存存取資料的電路的半導體記憶體元件
朴基豪
2006.10.11

TW I261198 B 同步多絮處理器、依據多數個操作絮在不同效能水平下操作的電腦程式產品、以及其操作方法
朴基豪
2006.09.01

Domestic Patents

KR 10-1978558 B1 센서 허브의 센싱 데이터 처리 방법 및 센서 인터페이스 제어 장치
박기호, 이승진, 기민관
2019.05.08

KR 10-1889101 B1 메모리 복사를 이용하여 영상을 복원하는 방법 및 장치
조진수, 박기호, 이원창, 이시화, 김도형, 송준호
2018.08.09

KR 10-1864831 B1 가상 캐시를 포함하는 메모리 및 그 관리 방법
박기호
2018.05.30

KR 10-1843243 B1 제로값을 피연산자로 갖는 연산자에 대한 연산을 스킵하는 연산 방법 및 연산 장치
박기호, 기민관
2018.03.22

KR 10-1824182 B1 전력 관리 기능을 갖는 프로세서 및 프로세서의 전력 관리 방법
박기호, 기민관, 선현수
2018.01.25

KR 10-1502998 B1 메모리 시스템 및 그 관리 방법
박기호
2015.03.10

KR 10-1469848 B1 메모리 시스템 및 그 관리 방법
박기호
2014.12.01

KR 10-1298171 B1 메모리 시스템 및 그 관리 방법
박기호
2013.08.13

KR 10-1263167 B1 메모리 셀에 대한 액세스 정보를 저장하는 반도체 메모리장치
박기호, 정건옥
2013.05.02

KR 10-1166803 B1 비휘발성 메모리 및 휘발성 메모리를 포함하는 메모리 시스템 및 그 시스템
박기호
2012.07.12

KR 10-1056460 B1 캐쉬 제어기 및 캐쉬 블록 교체 방법
박기호
2011.08.05

KR 10-1035077 B1 다이나믹 전압 스케일링에 따라 전력 소비 감소가 가능한반도체 시스템
박기호
2011.05.09

KR 10-0940260 B1 다이나믹 주파수 스케일링에 따라 동작 모드의 제어가 가능한 반도체 시스템 및 동작 모드 제어 방법
박기호
2010.01.27

KR 10-0912429 B1 고속 움직임 추정을 위한 영상 검색 방법
박기호, 박성배, 김신덕, 김정길, 이인직
2009.08.10

KR 10-0874949 B1 단일 명령 다중 자료 프로세서 및 그것을 위한 메모리 어레이 구조
박기호, 박성배, 김신덕, 박정욱, 박준규
2008.12.12

KR 10-0688503 B1 브랜치 목적 어드레스를 이용하여 캐쉬 웨이를 예측하는프로세서 및 그 방법
박기호, 이회진
2007.02.22

KR 10-0634384 B1 액세스 데이터를 저장하는 회로를 구비한 반도체 메모리 장치
박기호
2006.10.09

KR 10-0591769 B1 분기 예측 정보를 가지는 분기 타겟 버퍼
박기호
2006.06.13

KR 10-0594256 B1 동시 다중 쓰레딩 프로세서 회로, 동작하는 쓰레드들의수에 기초하여 다른 성능레벨들에서 동작하도록 구성되는컴퓨터 프로그램 제품 및 이들을 동작시키는 방법
박기호
2006.06.21

KR 10-0272165 B1 캐쉬 메모리 시스템 및 그의 운영 방법
한탁돈, 김신덕, 박기호
2000.08.23

KR 10-0146059 B1 미참조 선인출 캐쉬를 이용한 명령어 선인출 방법 및 그 회로
한탁돈, 박기호, 김신덕
1998.05.08